68-Pin Expansion Connector Pinouts

Daniel JB Clark ((no email))
Sat, 15 Oct 1994 21:27:35 -0400 (EDT)

(From one of the Digests, #42 I think)

Date: Fri, 30 Jul 1993 07:39:50 -0700
From: brian@piano.grot.starconn.com (Brian Smithson)
Subject: EXT connector pinout

For those who are really into hacking the UltraLite, here's the pinout
of the EXT connector (aka floppy/parallel peripheral port). The numbering
scheme is left as an exercise to the reader :-).

a1,3-7,b1,3-7 gnd signal ground
a2,b2 +5vds EXT eqip. detect signal
a8,b8 +5v +5v power to EXT from UltraLite
a9 dbm7 I/O data bus...
a10 dbm6
a11 dbm5
a12 dbm4
a13 dbm3
a14 dbm2
a15 dbm1
a16 dbm0
a17 gnd signal ground
a18 ab9 address bus (negative)...
a19 ab8
a20 ab7
a21 ab6
a22 ab5
a23 ab4
a24 ab3
a25 ab2
a26 ab1
a27 ab0
a28,a29 n/c
a30,b30 gnd signal ground
a31,b31 n/c
a32,b32 +5vacdc +5v power to EXT equip.
comes from AC adaptor through UltraLite
a33,b33 n/c
a34,b34 gnd signal ground
b9 rstp reset, active low
b10 irq2 interrupt request level 2, active high
b11 n/c
b12 irq6 interrupt request level 6, active high
b13 irq7 interrupt request level 7, active high
b14 gnd signal ground
b15 iow i/o write, active high
b16 ior i/o read, active high
b17 drq1 dma request level 1, active high
b18 dack1 dma acknowledge level 1, active high
b19 drq2 dma request level 2, active high
b20 dack2 dma acknowledge level 2, active high
b21 gnd signal ground
b22 mclk V30 system clock
b23 t/c terminal count (DMA), active high
b24 i/o chck i/o channel check, active high
b25 i/o chrdy i/o channel ready
high=cpu wait
low=cpu ready
b26 cpuaen address enable
high=cpu mode
low=dma mode
b27 dsrr recognition of EXT equip.
i/o port 1A2h (read only)
d7=high: exist
d7=low: none
b28 dssel UltraLite bus buffer control, active high
b29 n/c

-Brian Smithson

>>>>>>> My Question: Are these anything like "normal" FDD/Parellel port >>>>>>> pinouts? Anybody have "Normal" pinouts handy? <<<<<<< >>>>>>> Daniel JB Clark